MINISTRY OF EDUCATION OF THE RUSSIAN FEDERATION
ORYOL STATE TECHNICAL UNIVERSITY
Department of PTEiVS
COURSE WORK
on the topic of: " Technology for manufacturing semiconductor integrated circuit chips »
Discipline: “Materials Science and Electronic Materials”
Completed by a student of group 31-R
Kozlov A. N.
Head Koschinskaya E.V.
Eagle, 2004
Introduction
Part I. Analytical review
1.1 Integrated circuits
1.2 Requirements for semiconductor substrates
1.3 Characteristics of monocrystalline silicon
1.4 Rationale for the use of monocrystalline silicon
1.5 Technology for producing monocrystalline silicon
1.5.1 Obtaining silicon of semiconductor purity
1.5.2 Growing single crystals
1.6 Mechanical processing of monocrystalline silicon
1.6.1 Calibration
1.6.2 Orientation
1.6.3 Cutting
1.6.4 Grinding and polishing
1.6.5 Chemical etching of semiconductor wafers and substrates
1.7 Operation of dividing substrates into boards
1.7.1 Diamond scribing
1.7.2 Laser scribing
1.8 Breaking wafers into crystals
Part II. Calculation
Conclusion
The manufacturing technology of integrated circuits is a set of mechanical, physical, and chemical methods for processing various materials (semiconductors, dielectrics, metals), as a result of which an integrated circuit is created.
The increase in labor productivity is primarily due to the improvement of technology, the introduction of progressive technological methods, the standardization of technological equipment and tooling, and the mechanization of manual labor based on the automation of technological processes. The importance of technology in the production of semiconductor devices and ICs is especially great. It was the constant improvement of semiconductor device technology that led, at a certain stage of its development, to the creation of integrated circuits, and subsequently to their widespread production.
The production of ICs began around 1959, based on the planar technology proposed by that time. The basis of planar technology was the development of several fundamental technological methods. Along with the development of technological methods, the development of IS included research into the principles of operation of their elements, the invention of new elements, improvement of methods for purifying semiconductor materials, conducting their physical and chemical studies in order to establish such important characteristics as the limiting solubility of impurities, diffusion coefficients of donor and acceptor impurities, etc. .
In a short historical period, modern microelectronics has become one of the most important areas of scientific and technological progress. The creation of large and ultra-large integrated circuits, microprocessors and microprocessor systems made it possible to organize mass production of high-speed electronic computers, various types of electronic equipment, process control equipment, communication systems, automatic control and regulation systems and devices.
Microelectronics continues to develop at a rapid pace, both in the direction of improving semiconductor integrated technology and in the direction of using new physical phenomena.
1.6.1 Calibration
Calibration of single crystals of semiconductor materials. Ensures that they are given a strictly cylindrical shape and a given diameter. Calibration of semiconductor single crystals is most often carried out by the cylindrical grinding method on universal cylindrical grinding machines equipped with a diamond grinding wheel with a grain size designated 50/40 (the main fraction is 40 microns, and the amount of coarse fractions, 50 microns in size, is no more than 15%). Before the calibration operation, metal cones (“centers”) are glued to the ends of the single crystal using adhesive mastic so that their axis coincides with the longitudinal axis of the single crystal.
After calibration, a damaged layer with a depth of 50...250 μm is formed on the surface of the single crystal, depending on the longitudinal feed rate. Its presence at the periphery of substrates can cause the appearance of chips, and during subsequent high-temperature processing lead to the generation of structural defects propagating into the central regions of the substrate. To remove the damaged layer, semiconductor single crystals that have undergone calibration operations are subjected to chemical etching.
6.2 Orientation
During the growth of single crystals, a discrepancy between the ingot axis and the crystallographic axis is observed. To obtain plates oriented in a given plane, the ingots are oriented before cutting. The methods of crystal orientation are determined by their nature, the type of part and its functional purpose. Optically isotropic dielectrics are oriented to take into account the influence of the technological properties of the crystal on the accuracy of the part parameters. For anisotropic dielectrics, the position of the refractive and reflective surfaces of the part depends on the required conversion of the light flux. The orientation of semiconductors involves defining the crystallographic plane in which the material has specified electrical properties. The orientation of semiconductors is carried out by X-ray or optical methods.
The X-ray method is based on the reflection of X-rays from the surface of a semiconductor material. The reflection intensity depends on the density of packing of atoms on a given plane. A crystallographic plane more densely packed with atoms corresponds to a higher intensity of ray reflection. Crystallographic planes of semiconductor materials are characterized by certain angles of reflection of X-rays incident on them. The values of these angles for silicon: (111) -17°56", (110) - 30° 12", (100) - 44°23"
The X-ray diffractometric method is based on measuring the angle of reflection of characteristic X-ray radiation from an identified plane. For this purpose, general-purpose X-ray diffractometers are used, for example, type DRON-1.5, or X-ray installations, for example, type URS-50I (M), and others, equipped with X-ray goniometers and devices that ensure rotation of a horizontally located single crystal around an axis at a given speed.
When carrying out measurements, the X-ray beam incident on the end cut of the single crystal is directed at the Bragg reflection angle p. The X-ray counter (Geiger) is placed at an angle of 2p to the incident beam. If the oriented plane, for example (111), makes a certain angle, and with the end cut of the single crystal, then reflection from it can be obtained by rotating the single crystal at the same angle.
The reflection angle is determined relative to two mutually perpendicular axes, one of which lies in the plane of the drawing (Figure 3)
Figure 3 - Scheme of orientation of semiconductor single crystals using the X-ray method: 1-incident X-ray beam; 2- single crystal; 3 - reflected x-ray: 4 - Geiger counter
The optical method is based on the fact that etching figures appear on the semiconductor surface etched in a selective etchant, the configuration of which is determined by its crystallographic orientation. On the (111) surface, the etching figures have the shape of trihedral pyramids, and on the (100) surface, they are tetrahedral. When such a surface is equipped with a parallel beam of light, the reflected rays will form light figures on the screen.
Depending on how strongly the plane of the end cut of the single crystal is deviated from the plane (hkl), the light figure formed by the reflected beam of light will be closer or further from the center of the screen. By the magnitude of the deviation of the light figure from the zero division of the screen, the angle of deviation is determined, and the plane of the end of the single crystal from the plane (hkl). Then, turning the single crystal by 90°, another angle P is determined; After the orientation of the single crystal is completed, an arrow is applied to its end with a carbide cutter, the direction of which indicates in which direction from the end of the single crystal the required plane is deviated. The accuracy of orientation of semiconductor single crystals by the X-ray method is ± (2...6)", and by the optical method ±(15...30)".
1.6.3 Cutting
Table 2 - Comparative characteristics of abrasive materials
Diamond is the hardest material. When processing silicon, both natural and synthetic diamonds are used, which are inferior in mechanical properties to the former. Sometimes boron carbides B 4 C and silicon SiC are used, as well as electrocorundum Al 2 O 3. Currently, when cutting silicon ingots into wafers, metal disks with an internal diamond cutting edge are used as a cutting tool..
Figure 5 - Installation diagram for cutting with a diamond disc: a - internal cutting method; b - comb cutting method (1 - drum; 2 - disk; 3 - diamond coating; 4 - mandrel; 5 - plate; 6 - ingot)
The surface of the wafers obtained after cutting does not meet the requirements for the quality of the silicon surface using planar technology. Using an electron diffraction scanner, the presence of near-surface layers that do not have a monocrystalline structure is determined. The thickness of the damaged layer after cutting with a disk is 10 - 30 microns, depending on the rotation speed of the disk. Since in an IC the depth at which p-n junctions are located is units and tenths of a micron, the presence of damaged layers 10 - 30 microns thick is unacceptable. Microroughness on the surface should not exceed 0.02 - 0.1 microns. In addition, photolithography of wafer plane parallelism should be maintained at ±1 µm across the wafer diameter instead of 10 µm after cutting.
6.4 Grinding and polishing
To ensure the required quality, the surfaces of the plates must be further processed. This treatment consists of grinding and then polishing the plates. Grinding and polishing of the plates is carried out on precision surface grinding machines using abrasive materials with a grain size of about 40 microns (micropowders). Most often, groups of micropowders with grains of 14 microns or less are used. Table 3 shows the brands and grain sizes of the main fraction of the micropowders used. Micropowders M14, M10, M7, M5 are made from boron, silicon and electrocorundum carbides, micropowders of ASM grades are made from diamond.
Table 3 - Micropowders for grinding and polishing silicon wafers
Depending on the type of micropowder, the surface material of the grinder is selected. When grinding plates with M14-M15 micropowders, a glass grinder is used; when polishing with ASM micropowders, special grinders with a surface made of fabric materials are used. When processing plates, three heads with glued plates are installed on the working grinder. The heads are kept from moving around the grinder by special guide brackets with support rollers (Figure 6). Due to the friction force arising between the contacting surfaces of the working grinder and the heads, the latter rotate around their axes. This rotation of the heads creates conditions for uniform grinding or polishing.
Table 4 - Characteristics of micropowders
| Powder type | Thickness of the damaged layer, µm | Material removal rate, µm/min | Surface roughness class |
| M14 | 20 – 30 | 3 | 7 |
| M10 | 15 – 25 | 1,5 | 8 – 9 |
| ASM3/2 | 9 – 11 | 0,5 – 1,0 | 12 – 13 |
| ASM1/0.5 | 5 – 7 | 0,35 | 13 |
| ASM0.5/0.3 | Less than 3 | 0,25 | 13 – 14 |
| ASM0.3/0.1 | Less than 3 | 0,2 | 14 |
Figure 6 - Diagram of a surface grinding machine and location of heads : 1- dosing device with abrasive suspension ; 2- cargo ; 3- head ; 4- plates ; 5- grinder ; 6- guide roller
In general, mechanical processing of wafers that meet the requirements of planar technology leads to large silicon losses (about 65%).
6.5 Chemical etching of semiconductor wafers and substrates
It is accompanied by the removal of a surface layer with a mechanically damaged crystal structure, along with which the contaminants present on the surface are also removed. Pickling is a mandatory technological operation.
Acid etching of semiconductors, in accordance with chemical theory, occurs in several stages: diffusion of the reagent to the surface, adsorption of the reagent by the surface, surface chemical reactions, desorption of reaction products and their diffusion from the surface.
Etchants for which the slowest stages that determine the overall etching process are diffusion are called polishing. They are insensitive to physical and chemical inhomogeneities of the surface, smooth out roughness, leveling the microrelief. The etching rate in polishing etchants depends significantly on the viscosity and mixing of the etchant and depends little on temperature.
Etchants for which the slowest stages are surface chemical reactions are called selective. The etching rate in selective etchants depends on temperature, structure and crystallographic orientation of the surface and is independent of the viscosity and mixing of the etchant. Selective etchants with a large difference in etching rates in different crystallographic directions are usually called anisotropic.
Surface chemical reactions during polishing etching take place in two stages: oxidation of the surface layer of the semiconductor and conversion of the oxide into soluble compounds. When etching silicon, nitric acid plays the role of an oxidizing agent:
Hydrofluoric (hydrofluoric) acid, which is part of the etchant, converts silicon oxide into silicon tetrafluoride:
For etching, which gives a mirror surface of the plates, a mixture of the indicated acids is used in a ratio of 3:1, the etching temperature is 30...40 ° C, the etching time is about 15 s.
Breaking scribed plates is a very important operation. If even well-scribed plates are broken incorrectly, defects occur: scratches, chips, distortion of the crystal shape, etc.
7.1 Diamond scribing
The quality of scribing and subsequent breaking largely depends on the condition of the working part of the diamond cutter. Working with a cutter with a worn cutting edge or tip leads to chipping during scribing and poor-quality breaking. Typically, scribing is performed with cutters made from natural diamond, which are more expensive compared to cheaper synthetic diamond cutters. Cutters have become widespread, having a cutting part in the shape of a trihedral or truncated tetrahedral pyramid (Figure 7, c), the cutting elements of which are its ribs.
7.2 Laser scribing
During laser scribing (Figure 8), separation marks between finished structures are created by the evaporation of a narrow strip of semiconductor material from the surface of the wafer as it moves relative to the focused laser beam. This leads to the formation of relatively deep (up to 50...100 µm) and narrow (up to 25...40 µm) grooves in the plate. The groove, narrow and deep in shape, plays the role of a mechanical stress concentrator. When the plate breaks, the resulting stresses lead to the formation of cracks at the bottom of the groove, propagating through the entire thickness of the plate, resulting in its separation into individual crystals.
Along with the creation of a deep dividing groove, the advantage of laser scribing is its high productivity (100...200 mm/s), the absence of microcracks and chips on the semiconductor wafer. A pulsed optical quantum generator with a pulse repetition rate of 5...50 kHz and a pulse duration of 0.5 ms is used as a cutting tool.
Figure 8 - Scheme of laser scribing of a semiconductor wafer
8 Breaking wafers into crystals
The breaking of wafers into crystals after scribing is carried out mechanically by applying a bending moment to it. The absence of crystal defects depends on the applied force, which depends on the ratio of the overall dimensions and thickness of the crystals.
Figure 10 - Breaking a semiconductor wafer by rolling between rollers: 1 - wafer; 2 - elastic roller; 3 - protective film; 4 - steel roller; 5 - carrier film
Plate 1, located with the marks upward, is rolled between two cylindrical rollers: the upper elastic (rubber) 2 and the lower steel 4. To maintain the original orientation of the crystals, the plate is fixed on a thermoplastic or adhesive carrier film 5 and its working surface is protected with polyethylene or lavsan film 3. The distance between the rollers, determined by the thickness of the plate, is established by moving one of them.
When breaking on a spherical support (Figure 11), plate 2, located between two thin plastic films, is placed with marks down on rubber diaphragm 3, spherical support 1 is brought in from above and, using the diaphragm, the plate is pressed against it using pneumatic and hydraulic methods, which breaks into individual crystals . The advantages of this method are simplicity, high productivity (breaking takes no more than 1-1.5 minutes) and single-stage nature, as well as fairly high quality, because the crystals do not move relative to each other.
Table 5 - Depth of the damaged layer of silicon wafers after various types of mechanical treatment
Part II. Calculation
DETERMINATION OF TOTAL ALLOWANCE FOR MECHANICAL PROCESSING
Z=Z GSh +Z TS +Z PP +Z FP,
where Z is the sum of allowances for processing, Z GSh is the allowance for rough grinding, Z TS is the allowance for fine grinding, Z PP is the allowance for preliminary polishing, Z FP is the allowance for finishing polishing.
m ∑ = ρ* l ∑ * S,
where S is the area of the workpiece, ρ= 2.3 g/cm is the density of silicon.
m ∑ = 2.3* 10 3 * 696.21* 10 -6 * 0.0177 = 0.0283 kg
Weight of processed workpiece:
m= 2.3* 10 3 * 550* 10 -6 * 0.0177 = 0.0223 kg
M P = (N* m) / n,
where M P is the useful mass of the material.
k IM = M P / M,
where k IM is the material utilization coefficient.
K MI =11.903/16.479 = 0.722
Conclusion
In the course work, a technological process was developed for the production of semiconductor integrated circuit chips from monocrystalline silicon. At the same time, the material utilization coefficient for the considered production conditions was 0.722. This suggests that the manufacturability of production is at a fairly high level, especially at the stage of processing workpieces, since the yield suitable for processing is 81%. The material utilization rate is quite high, although this technological process was introduced into production relatively recently.
Bibliography
1. Berezin A.S., Mochalkina O.R.: Technology and design of integrated circuits. - M. Radio and Communications, 1983. - 232 p., ill.
2. Gotra Z. Yu. Technology of microelectronic devices: Handbook. - M.: Radio and Communications, 1991. - 528 p.: ill.
3. Koledov L. A. Technology and designs of microcircuits, microprocessors and microassemblies: Textbook for universities. - M.: Radio and communication, 1989. - 400 pp., ill.
4. Design and technology of microcircuits. Course design.: ed. L. A. Koledova. - M.: Higher. school, 1984. - 231 p., ill.
5. StepanenkoI. P. Fundamentals of microelectronics: Textbook for universities. - 2nd ed., revised. and additional - M.: Laboratory of Basic Knowledge, 2000 - 488 pp., ill.
6. Chernyaev V. N. Technology of production of integrated circuits and microprocessors: Textbook for universities. - 2nd ed., revised. and additional - M.: Radio and Communications, 1987. - 464 p.: ill.
Introduction
1.analytical review 2. Technological part 1 Description of the technological process 2 Selecting a class of production premises 3 Basic materials and reagents 4 Basic technological operations 4.1 Cleaning the substrate 4.2 Thermal oxidation 4.3 Lithographic processes 4.4 Ion implantation 4.5 Metallization 4.6 Interlayer insulation 3. engineering and economic calculations Conclusion Introduction Integrated circuit technology has developed at an extremely rapid pace and has achieved incredible success. Electronics has gone through several stages of development, during which several generations of the element base have changed: discrete electronics of electric vacuum devices, integrated electronics of microcircuits (microelectronics), integrated electronics of functional microelectronic devices (functional microelectronics). Currently, it plays a decisive role in improving almost all sectors of the national economy (integrated circuits are used in computers, computer-aided design systems, industrial robots, communications, etc.). The technological processes used in the manufacture of semiconductor integrated circuits (ICs) are of a group nature, i.e. A large number of ICs are manufactured simultaneously. Many technological operations make it possible to process up to 200 wafers, which allows the simultaneous production of over a million electronic devices. To realize the great possibilities of planar technology, it is necessary to fulfill a considerable number of general production requirements and certain technological conditions that ensure the production of high-quality samples of semi-finished products at all technological stages. And this is impossible without the use of especially pure basic and auxiliary materials, allocated to a special class “for semiconductor production,” precision technological and control equipment, and production facilities that meet such high requirements of technological hygiene that are not found in any other industries. The goal of this project is to study modern technological techniques in the production of solid-state electronics products and to develop an end-to-end technological process for manufacturing a MOS transistor with a Schottky diode. transistor integrated circuit 1. Analytical review An insulated gate field effect transistor is a field effect transistor whose gate is electrically separated from the channel by a layer of dielectric. An insulated gate field effect transistor consists of a semiconductor wafer (substrate) with a relatively high resistivity, in which two regions with opposite types of electrical conductivity are created). Metal electrodes are applied to these areas - source and drain. The surface of the semiconductor between the source and drain is covered with a thin layer of dielectric (usually a layer of silicon oxide). A metal electrode - a gate - is applied to the dielectric layer. The result is a structure consisting of a metal, a dielectric and a semiconductor (Figure 1). Therefore, field-effect transistors with an insulated gate are often called MOS transistors or MOS transistors (metal-oxide (oxide)-semiconductor). Figure 1 - Topology and main elements of a MOS transistor The MOS-IC manufacturing technology occupies a dominant position among the manufacturing processes of semiconductor ICs. This is explained by the fact that ICs based on MOS transistors make up a significant part of the main microelectronics products for various functional purposes. Due to their high reliability and high functional complexity, MOS-ICs have smaller geometric dimensions than ICs based on bipolar transistors. The manufacturing technology of MOS-IC chips is in many ways similar to the technology of bipolar ICs. The difference is due to a number of design and technological features of the MOS-ICs themselves. There are MOS transistors with built-in and induced channel: · On-channel MOSFETs have a special on-chip channel whose conductivity is modulated by gate bias. In the case of a p-type channel, the positive channel repels holes from the channel (depletion mode), and the negative channel attracts (enrichment mode). Accordingly, the channel conductivity either decreases or increases compared to its value at zero bias. · In induced-channel MOSFETs, a conductive channel occurs between the heavily doped source and drain regions and, therefore, appreciable drain current appears only at a certain polarity and at a certain value of gate voltage relative to the source (negative for the p-channel and positive for the n-channel). This voltage is called threshold. The first in industrial production were p-MOS-ICs, because The production of n-MOS-ICs was complicated by the appearance on the surface of p-Si during thermal oxidation of an inverse n-layer, which electrically connects the elements of the IC. But currently n-channel ICs dominate production. Transistors with channel electronic conductivity have better characteristics, since the mobility of electrons in silicon significantly exceeds the mobility of holes. MDP-ICs are manufactured using planar technology. The most critical moments in the technological process are: creating a gate dielectric, precise alignment of the gate with the channel, and obtaining structures with a short channel length. For a field-effect transistor with an insulated gate, it can be combined with a Schottky diode. An integrated Schottky diode is a semiconductor-metal contact on which a so-called Schottky barrier is formed. Transitions of this type, made taking into account certain requirements, are characterized by such effects as asymmetry of the current-voltage characteristic and the presence of a barrier capacitance. To obtain such transitions, the metal deposited as an electrode on the surface of the electronic semiconductor must have a work function less than the work function of the semiconductor; for an electrode deposited on the surface of a hole semiconductor, a metal with a higher work function is required (Figure 2). Figure 2 - Band diagram of Schottky barter formation at the point of contact between metal and p-type semiconductor In this case, a layer enriched with majority carriers is formed in the semiconductor at the interface with the metal, providing high conductivity of the junction regardless of the direction of the current. In general, the manufacture of an MOS transistor with a Schottky diode does not require the introduction of additional technological operations. 2. Technological part 1 Description of the technological process Figure 3 - Sequence of technological operations for the production of a MOS transistor with a Schottky diode Boron is introduced into the original wafer using ion implantation to obtain a p-type substrate (Figure 3, a). After this, using photolithography and ion implantation of phosphorus, areas with an increased content of donors are formed (Figure 3, c-e). Subsequently, an additional layer of silicon dioxide is grown. Since the temperature at this stage is high, phosphorus impurities during this operation are more evenly distributed throughout the thickness of the near-surface layer of the substrate (Figure 3, g). Using regular photolithography, we remove silicon oxide in the area separating the drain and source of the future transistor (Figure 3h). Now the most important operation in the entire production cycle is growing the gate dielectric (Figure 3, i). Now all that remains is to form the drain, source and gate electrodes, as well as the Schottky junction. Now we will show this metallization in a simplified manner (Figure 3, j), and then we will consider in more detail the principles of its formation (section 2.4.5). 2 Selecting a class of production premises The modern requirements for cleanliness classes of clean rooms and clean zones are based on the standards defined in the US Federal Standard FS209E. The prepared draft Russian standard is harmonized with this US standard. The purity criterion is the absence or minimum number of contaminant particles that, being on the surface of the wafer, can cause either defects in the grown layers or cause short circuits in nearby closely located IC elements. Table 1 - Cleanliness classes for airborne particles for clean rooms Cleanliness class Maximum permissible count concentration of particles N (pcs/m 3) size equal to and greater than (µm)0,10,20,30,51,0Class 1 ISO102---Class 2 ISO10024104-Class 3 ISO1000237102358Class 4 ISO100002370102035283Class 5 ISO10000023700102003 520832Class 6 ISO1000000237000102000352008320Class 7 ISO---35200083200Class 8 ISO---3520000832000Class 9 ISO---352000008320000 Quantitative criterion - critical particle size - one third of the minimum geometric horizontal size of the IC element: Thus, you can choose a clean room that corresponds to cleanliness classes from ISO 1 to ISO 6. Also focusing on cost, we select cleanliness class ISO 2, for which the maximum permissible concentration of airborne particles equal to or greater than the size under consideration is 0.2 microns ( number of particles in 1m3 of air) is: where N is the ISO cleanliness class number; D is the particle size under consideration, microns. 3 Basic materials and reagents For many years, monocrystalline silicon has remained the main semiconductor material used to manufacture integrated circuits. Silicon wafers are the basis in whose surface layers semiconductor regions with specified electrical characteristics are created. Dielectric layers are formed on the silicon surface by oxidation of the semiconductor material itself or by the application of dielectrics from external sources; structures of multilayer metallization, protective, stabilizing layers, and so on are formed. The requirements for silicon wafers have been worked out in detail; there is a whole catalog of international standards of the SEMI association; at the same time, the requirements for silicon continue to constantly increase, which is associated with the constant desire to reduce the cost of the final product - integrated circuits. Below are some geometric characteristics of silicon wafers in accordance with technical specifications ETO.035.124TU, ETO.035.206TU, ETO.035.217TU, ETO.035.240TU, ETO.035.578TU, PBCO.032.015TU. Plate diameter 100mm. The (100) orientation of the silicon substrate has the advantage over the (111) orientation of higher electron mobility due to the low density of surface states at the silicon-insulator interface. Plate thickness 500 microns. The spread of thickness values in a batch is ±10 µm. The spread of thickness values across the plate is ±12 µm. Deflection 20 microns. Flatness deviation ±5 µm. High requirements for impurities and mechanical particles are placed on deionized water. Table 2 shows extracts from the guidance material of the international association SEMI indicating the recommended parameters of ultrapure water for the production of semiconductor integrated circuits with a minimum element size of 0.8-1.2 microns. The corresponding indexing of liquid reagents according to SEMI standards is written as SEMI C7. The value of the electrical resistivity parameter of water should be close to the theoretical value of 18.2 MOhm cm. Content of oxidizable organic matter, ppb<10Содержание тяжелых металлов, ppb<3Частиц/литр 0,1-0,2U 0,2-0,3U 0,3-0,5U >0.5U<1500 <800 <50 <1Бактерии/100мл<5SiO23Ion content, ppb Na +K +Cl -Br -NO 3-SO 42-Total number of ions, ppb 0.025 0.05 0.025 0.05 0.05 0.2<0.2Сухой остаток, ppm<0,05
In addition to the parameters indicated in the table, SEMI recommendations provide data on the presence of traces of a number of metals in water. The analysis is carried out for the content of the following metals: Li, Na, K, Mg, Ca, Sr, Ba, B, Al, Cr, Mn, Fe, Ni, Cu, Zn, Pb. For SEMI C7 grade water, for all of these elements without exception, the permissible trace concentrations range from 0.001 to 0.005 ppb. The level of purity of liquid chemicals used in the production of integrated circuits is determined by a series of international standards and has various gradations in accordance with the level of complexity of integrated circuits. "Grade 2" has a standard designation starting with the symbols SEMI C7. Reagents having a purity level of “Grade 2” are used in the manufacture of integrated circuits with design standards in the range of 0.8-1.2 microns, which corresponds to the requirement of the task. In "Grade 2" reagents, foreign particles measuring 0.5 microns and larger are controlled. In almost the entire range of reagents, the maximum norm is 25 particles per 1 ml of reagent. The specifications for such reagents indicate a trace metal content of 5-10 ppb. In addition to standards for high purity chemicals, specifications in the form of guidelines have been developed. In accordance with them, three levels (tiers) of cleanliness requirements have been formed: A, B, C (in English spelling - Tier A, Tier B, Tier C). Level A meets the requirements of the SEMI C7 standard. Accordingly, reagents for this technological process must meet Tier A. Gases play an exceptional role in integrated circuit manufacturing technology. Almost all technological processes take place in a gaseous environment, and the problem of creating a “pollution-free” production of semiconductor devices is to a large extent a problem of gas purity. There are two types of gaseous media: carrier gases and gases of chemical reactions in technological processes. The partial pressure of carrier gases is, as a rule, high, and therefore their purity, taking into account the high concentration in the working gaseous environment, is especially critical in technology. Table 3 - Gases in IC manufacturing processes No. Name Chemical formula Content of main substance, % Total content of impurities (ppm parts mole/mol) 1 Ammonia NH 399.998122ArgonAr99.999900.953ArsineAsH 399.94533 (of which 500 ppm is hydrogen H 2)4Boron trichlorideBCl 399.9995 (by weight in the liquid phase)5 (by weight in the liquid phase)5Boron trifluorideBF 399.00.94% - gases insoluble in water, 200 ppm - SiF 4. Other impurities - 28 ppm.6 Carbon tetrafluorideCF 499.99730, including 20 - N 2, 5 - O 27DiboranB 2H 699.81012, of which 500 are CO 2 300 - B 4H 10- tetraborane 50 - H 250 - N 28DichlorosilaneH 2SiCl 299The main impurities are other chlorosilanes in the liquid phase9HeliumHe99.99954.510HexafluoroethaneC 2F 699.9963911 HydrogenH 299.99972.812 Hydrogen chlorideHCl99.9972813 Fluoric anhydrideHF99.94525, including 200 - water vapor by volume14 NitrogenN 299.999990.115 Nitrogen trifluorideNF 399.81000, incl. CF 4- 500, CO - 130, N 2-100, O 2- 10016 Nitrous oxideN 2O99.99726, including 10 - N 217OxygenO 299.998218PhosphinePH 399.98181, including 100 - H 2, 50 - N 219MonosilaneSiH 499.9945920Silicon tetrachlorideSiCl 499.6Main impurities: SiH 2Cl 2- 0.2% in liquid phase, SiHCl 3- 0.2% in liquid phase 21 Sulfur hexafluorideSF 699.97209, including 100 - CF 422Tungsten hexafluorideWF 699.99639, including 20 - HF23 Chlorine trifluorideClF 3
4 Basic technological operations 2.4.1 Cleaning the substrate It is clear that any substrate contains some amount of contaminants. These can be dust particles, molecules of various substances, both inorganic and organic. Dust particles are removed either by mechanical brush or ultrasonic cleaning. Methods using centrifugal jets are used. The chemical cleaning procedure is usually carried out after the elimination of inorganic molecules and atoms, and consists of removing organic contaminants. The normal cleaning procedure is carried out in mixture H 2O-H 2O 2-NH 4OH, which ensures the removal of organic compounds due to the solvating effect of ammonium hydroxide and the oxidizing effect of hydrogen peroxide. To remove heavy metals, use solution H 2O-H 2O 2-HCl. Such cleaning of substrates is carried out at a temperature of ~80 º C for 10-20 minutes, after which they are washed and dried. 4.2 Thermal oxidation The oxidation of semiconductors is understood as the process of their interaction with oxidizing agents: oxygen, water, ozone, etc. A layer of silicon dioxide is usually formed on a silicon wafer due to the chemical interaction of silicon and oxygen atoms in the near-surface region of the semiconductor. Oxygen is contained in the oxidizing environment with which the surface of the silicon substrate, heated in an oven to a temperature of 900 - 1200 ° C, is in contact. The oxidizing medium can be dry or wet oxygen. A schematic view of the installation is shown in Figure 4 (in modern installations, the plates in the substrate holder are located vertically). Figure 4—Thermal oxidation process installation diagram Equipment requirements: 1)temperature of the substrate holder controlled with an accuracy of 1 degree; 2)ensuring a smooth increase and decrease in temperature in the reactor (two-stage heating); )absence of foreign particles in the reactor (the substrate holder is first inserted into the reactor pipe and then lowered to the bottom); )the absence of foreign impurities, in particular, sodium ions on the internal surface of the reactor (in order to remove them, the reactor pipe is pre-purged with chlorine); )ensuring the introduction of silicon wafers into the reactor immediately after their chemical cleaning. The chemical reaction occurring on the surface of a silicon wafer corresponds to one of the following equations: · oxidation in a dry oxygen atmosphere (dry oxidation): Si TV +O 2= SiO 2;
· oxidation in water vapor (wet oxidation): Si TV +2H 2O = SiO 2+ 2H 2;
· thermal oxidation in the presence of chlorine (chlorine oxidation); · oxidation in water vapor at elevated temperature and pressure (hydrothermal oxidation). At the same temperature, the diffusion coefficient of water in silicon dioxide is significantly higher than the diffusion coefficient of oxygen. This explains the high growth rates of the oxide in moist oxygen. Growing films only in humid oxygen is not used due to the poor quality of the oxide. Better films are obtained in dry oxygen, but their growth rate is too low. For masking during local treatments, oxidation is carried out in the dry-wet-dry oxygen mode. To form the gate dielectric of MOS structures, dry oxygen is used, because The films are of higher quality. 4.3 Lithographic processes The main purpose of lithography in the manufacture of microcircuit structures is to obtain contact masks with windows on the surface of the plates that correspond to the topology of the technological layers being formed, and further transfer of the topology (pattern) from the mask to the material of this layer. Lithography is a complex technological process based on the use of phenomena occurring in resists during actinic irradiation. Resists whose solubility in the developer increases after irradiation are called positive. Negative resists after irradiation become practically insoluble in the developer. Standardly in the electronics industry, optical lithography is used - photolithography (Figure 5), for which photoresists are used that are sensitive to actinic radiation with a wavelength from 200 to 450 nm. Photoresists are complex polymer compositions containing photosensitive and film-forming components, solvents and special additives. The project uses a positive, high-quality and stable photoresist FP-20F, intended for the implementation of contact and projection photolithographic processes in the production of semiconductor devices and integrated circuits. Accordingly, a weak aqueous solution of KOH or NaOH can be used for etching. The most optimal way to apply photoresist is centrifugation. The substrate is fixed on a horizontal centrifuge. 1-5 ml of photoresist is applied to the substrate (depending on the size of the substrate). The centrifuge is rotated to a speed of 1000-3000 rpm (depending on the brand of photoresist). Rotation continues for 1-2 minutes until a photoresist film is formed, while the solvent evaporates. Figure 5 - Scheme of the main operations of the photolithographic process There are several exposure methods; in the project we will use non-contact (Figure 6). Projection printing completely eliminates damage to the template surface. An image of the topological pattern of the template is projected onto a resist-coated plate, which is located at a distance of several centimeters from the template. Light source; 2- optical system; 3- template; Photoresist; 5- silicon wafer. Figure 6—Scheme of projection printing To achieve high resolution, only a small portion of the template design is displayed. This small reflected area is scanned or moved across the surface of the wafer. In scanning projection printing devices, the template and plate move synchronously. When drying photoresist, it is very important to choose the right temperature and time. Drying of the photoresist will be carried out by the most common method - IR radiation. In this case, the solvent is removed evenly throughout the thickness of the resist layer and its compaction does not occur, and the drying time is reduced to several minutes. 4.4 Ion implantation Doping of semiconductor materials in order to obtain specified electrical parameters of the layers when forming a certain geometric structure of the IC remains the most important technological task. There are two types of doping: diffusion (includes the stages of impurity driving and subsequent acceleration) and ionic. The most common is ion implantation (ion doping) as the process of introducing ionized atoms into a target with energy sufficient to penetrate into its near-surface regions (Figure 7). This method is distinguished by its versatility (any impurity can be introduced into any solid), the purity and accuracy of the alloying process (the ingress of uncontrolled impurities is virtually eliminated) and low process temperatures. Ion source; 2 - mass spectrometer; 3 - diaphragm; 4 - high voltage source; 5 - accelerating tube; 6 - lenses; 7 - lens power supply; 8 - vertical beam deflection system and beam shutdown system; 9 - horizontal beam deflection system; 10 - target for absorption of neutral particles; 11 - substrate. Figure 7 - Scheme of the ion doping installation During ion implantation, a number of undesirable effects appear, such as the channeling effect, amorphization of the near-surface layer of the substrate, and the formation of radiation defects. The channeling effect is observed when an ion enters the free space between rows of atoms. Such an ion gradually loses energy due to weak sliding collisions with the channel walls and eventually leaves this region. The distance traveled by an ion in a channel can be several times greater than the path length of an ion in an amorphous target, which means that the impurity distribution profile is uneven. When ions are introduced into a silicon crystalline substrate, they are subject to electronic and nuclear collisions, however, only nuclear interactions lead to displacement of silicon atoms. Light and heavy ions interact with the substrate differently. Light ions, when introduced into a target, initially experience mainly electronic braking. There is a hidden concentration maximum in the profile of the distribution of displaced atoms over the depth of the substrate. When heavy ions penetrate, they immediately begin to be strongly inhibited by silicon atoms. Heavy ions displace a large number of target atoms from crystal lattice sites near the substrate surface. In the final profile of the density distribution of radiation defects, which repeats the distribution of the free paths of knocked-out silicon atoms, there is a wide hidden peak. For example, light ions 11B experience mainly electronic braking, heavy ions 31P or 75As - inhibited by silicon atoms. In this regard, after ion doping, it is necessary to carry out post-implantation annealing in order to restore the near-surface region of the target. We will form the drain and source regions by introducing phosphorus, and to obtain a p-type substrate, we will dope the initial substrate with boron. 4.5 Metallization Metallization completes the process of formation of semiconductor structures. For each IC, it is advisable to perform metallization from one material. The metallization process consists of implementing low-resistance interconnects and creating low-resistance contacts to highly doped p- and n-type regions and polycrystalline silicon layers. According to the assignment for the course project, it is necessary to form 3 layers of metallization. This metallization more fully meets the requirements, but is less technologically advanced, because contains more than one layer of metal. Refractory metals, especially molybdenum and vanadium, are most often used as the first layer of metallization on the oxide. They have greater conductivity than other refractory metals, they are characterized by high stability, good adhesion, and are easily etched by photolithography. They must have low solubility in the substrate material and create good ohmic contact with the semiconductor and a low threshold voltage. The second layer is usually aluminum, and in especially critical devices - gold. It must be highly conductive. The last metallization layer in the order of application, called the conductive layer, must have good electrical conductivity and ensure high-quality connection of the contact pads to the housing terminals. Copper, aluminum, and gold are used for conductive layers. There are many methods for producing metal films. Obtaining high-quality, uncontaminated films using thermal vacuum deposition is difficult. Aluminum films obtained by thermal vacuum evaporation have a large unevenness of grain sizes and a high concentration inside the grains. Their subsequent heat treatment leads to the migration of metal atoms and their accumulation around large particles with the formation of high tubercles. Obtaining patterns on such films by photolithography leads to large edge irregularities due to the anisotropy of etching along grain boundaries. Therefore, to obtain metallization lines of very small width, thermal vacuum processes are abandoned. The method of chemical deposition of films from a vapor-gas mixture is more often used in laboratory conditions. Electron beam, despite the fact that it complicates the design of the installation, can reduce film contamination and increase process productivity (Figure 8). The optimal film growth rate is 0.5 µm/min. Using this method, films of aluminum and its alloys, as well as Si, Pd, Au, Ti, Mo, Pt, W are applied. The benefits of electron beam evaporation include: · the ability to use sources of large mass (no reboot required when applying thick films); · the possibility of sequential application of various films from adjacent sources located in the same chamber; · high film growth rate; · possibility of spraying refractory materials. The Schottky barrier, in terms of its functions, does not belong to metallization, but according to its formation technology, it can be classified as metallization, because it is similar to obtaining ohmic contacts to active regions. The most important stage in the formation of Schottky barriers is the selection of a metal-semiconductor pair and optimal modes. So, for the contact layer we will use platinum silicide, which will be applied by electron beam evaporation by joint evaporation from two sources. The Schottky barrier will be provided by an alloy of titanium and tungsten deposited on silicon using the same method. Essentially, this alloy will be similar to the heavily alloyed region. For the conductive layer, we use aluminum, also deposited by electron beam evaporation. 4.6 Interlayer insulation Multi-level metallization is used for LSI and VLSI. An increase in the number of elements also increases the area of inter-element connections, so they are placed in several levels, separated by insulating layers and interconnected in the right places. Insulating dielectric films must have a high breakdown voltage, low dielectric constant and losses, minimal chemical interaction with adjacent films, low levels of mechanical stress, low density of associated electrical charge, high chemical stability and manufacturability when producing films and creating patterns. The presence of through microholes, which can lead to a short circuit between the metallization layers, is unacceptable. The technology of multi-level metallization includes the formation of the first level of metallization, obtaining an insulating layer with the subsequent opening of inter-level contact windows, the formation of a second layer of metallization, etc. Many commercially produced ICs are made on the basis of aluminum metallization with insulating layers of SiO 2. Silicon dioxide films can be deposited with or without alloying additives. The most important parameter during SiO deposition 2- reproducibility of the relief (Figure 9). Figure 9-Conformal reproduction. The thickness of the film on the walls of the step does not differ from the thickness on the bottom and surface. Due to rapid surface migration In this project, undoped silicon dioxide applied by chemical vapor deposition is used as an insulating film between multi-level metallization (Figure 10). The latter is based on the use of the phenomenon of pyrolysis or chemical reactions in the formation of films of insulating material. Figure 10 - Installation for film formation by chemical vapor deposition at normal pressure Monosilane SiH is used as a reactive gas. 4and oxygen, and nitrogen as a buffer gas. SiH 4+O 2→ SiO 2+ 2H 2
This process is the lowest temperature for obtaining high-quality dielectric layers of SiO 2(the reaction is carried out in the temperature range 200-400 º WITH). The disadvantage is that silane is flammable and explosive. The films are formed very clean, but due to low temperatures they are loose. To avoid this, it is necessary to strictly regulate the concentration of silane in the gas phase and supply it directly to the surface of the plates, preventing the growth of SiO 2in the gas phase. 3. engineering and economic calculations Project topic: Development of a technological process for manufacturing semiconductor integrated circuits Technology type: MOSFET with Schottky diode Substrate material: Si Initial data for the project: Crystal (chip) size 10x10 mm2
Minimum design standard for an IP element 0.3µm Density of defects per layer 0.1def/cm2
Number of metallization layers 1
The percentage of yield of suitable structures on the plate (Y) is calculated using the following formula: where D0 is the specific density of defects per photolithography, def/cm2; A is the active area of the crystal, cm2; F is the number of photolithographic processes in the full technological cycle of IC manufacturing. The calculation of the total volume of production of suitable products is carried out based on the initial data. Yield of suitable structures on the plate: , where Apl is the active area of a plate with a diameter of 100 mm, A is the area of the element, cm2. Annual production volume when launching Z=300 wafers per day, provided that the percentage of yield of suitable products in assembly operations is W=95%: Table. Calculation of the threshold voltage of a MOS transistor. N a , cm -31∙1016 => 1∙1022m -3W H , µm1.5 = 1.5∙10 -6mt ox , nm40 => 4∙10 -8mL H , µm1.5 = 1.5∙10 -6mL, µm1.5 => 1.5∙10 -6mU DD , B3W, µm16 => 1.6∙10 -5m ε Si ,11,9μ n 0.15ε Si02 3.9ε 08.85∙10-12F/m 2
8.6∙10-4 F/m where, is the surface potential. where, is the voltage drop across the oxide layer. CONCLUSION This course work examines the manufacturing technology of semiconductor integrated circuit boards. A semiconductor integrated circuit is a microcircuit whose elements are made in the near-surface layer of a semiconductor substrate. These ICs form the basis of modern microelectronics. The crystal dimensions of modern semiconductor integrated circuits reach mm2; the larger the crystal area, the more multi-element IC can be placed on it. With the same crystal area, you can increase the number of elements by reducing their sizes and the distances between them. By using a different type of gate dielectric, other metals when forming contacts with silicon, and other insulating layers, it is possible to obtain more complex circuits with even smaller element sizes. List of sources used 1.Yezhovsky Yu.K. Fundamentals of thin-film materials science and technology of integrated devices: Textbook/ SPbGTI.- SPb., 2005.-127p. 2.Integrated devices of radio electronics UMK, SZTU, St. Petersburg 2009 .